# 抢答器

[抢答器.doc](%E6%8A%A2%E7%AD%94%E5%99%A8%204e6f2b7bc52f4a9396d63c320dceed30/%E6%8A%A2%E7%AD%94%E5%99%A8.doc)

```vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity selector is
port(
	clock : in std_logic;
	clk : in std_logic;
	rst : in std_logic;
	input_vector : in std_logic_vector(3 downto 0);
	output_vector : out std_logic_vector(3 downto 0);
	time_out : out std_logic_vector(3 downto 0) :="0000"
);
end selector;
architecture behave of selector is
signal enable : std_logic := '0';
signal counter : integer := 0;
signal time_count : std_logic_vector(3 downto 0):= "0000";
begin

process(clock, clk, rst)
begin
	if(clock='1' and clock'event) then
		if(rst='1') then
			enable <= '0';
			output_vector<= "0000";
			time_out <= "0000";
			time_count <= "0000";
			counter <= 0;
		elsif(clk='1') then
			enable <= '1';
			output_vector<= "0000";
		elsif(enable='1') then
			if(input_vector(0)='1') then
				output_vector <= "0001";
				time_out <= time_count;
				enable <= '0';
			elsif(input_vector(1)='1') then
				output_vector <= "0010";
				time_out <= time_count;
				enable <= '0';
			elsif(input_vector(2)='1') then
				output_vector <= "0100";
				time_out <= time_count;
				enable <= '0';
			elsif(input_vector(3)='1') then
				output_vector <= "1000";
				time_out <= time_count;
				enable <= '0';
		end if;
		if(counter=1000000) then
			counter <= 0;
			if (time_count /= "1001") then
				time_count <= time_count + 1;
			elsif (time_count = "1001") then
				time_count <= time_count;
			end if;
		else
			counter <= counter + 1;
			end if;
		end if;
	end if;
end process;

--			time_out <= time_count;
end behave;
```