# 摩尔码

[摩尔码.doc](%E6%91%A9%E5%B0%94%E7%A0%81%203eef5e1df0704337820887a3ca142b81/%E6%91%A9%E5%B0%94%E7%A0%81.doc)

- 基础需求

```vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moers is
port(
	clock : in std_logic;
	clk : in std_logic;
	lighten : out std_logic_vector(1 downto 0) := "00"
);
end moers;
architecture behave of moers is
signal counter : integer := 0; -- 0 代表设置，1代表倒计时
signal second_counter : integer := 0;
begin

process(clock, clk)
begin
	if rising_edge(clock) then
        if (clk = '1') then
            if(counter=1000000) then
                counter <= 0;
                if (second_counter = 0) then
                    second_counter <= 1;
                    lighten <= "10";
                end if;
            else
                counter <= counter + 1;
					 if (second_counter = 0) then
						lighten <= "01";
					 end if;
            end if;
        else
            counter <= 0;
            second_counter <= 0; 
				lighten <= "00";
        end if;
	end if;
end process;
end behave;
```

```vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moers is
port(
	clock : in std_logic;
	clk : in std_logic;
	lighten : buffer std_logic_vector(1 downto 0) := "00"
);
end moers;
architecture behave of moers is
signal counter : integer := 0; -- 0 代表设置，1代表倒计时
signal second_counter : integer := 0;
begin

process(clock, clk)
begin
	if rising_edge(clock) then
        if (clk = '1') then
            if(counter = 1000000 and second_counter = 0) then
                counter <= 0;
					 second_counter <= 1;
                if (lighten = "01") then
                    lighten <= "10";
                end if;
            else
                counter <= counter + 1;
					 if (second_counter = 0) then
						lighten <= "01";
					 end if;
            end if;
        else
            counter <= 0;
            second_counter <= 0; 
				lighten <= "00";
        end if;
	end if;
end process;
end behave;
```

- 扩展功能

```vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity moers_complex is
	port(
		clk: in std_logic;
		clock: in std_logic;
		long: buffer std_logic;
		short: buffer std_logic;
		rst: in std_logic;
		display: out std_logic_vector(3 downto 0);
        state: buffer std_logic_vector(4 downto 0):="00000"
	);
end moers_complex;

architecture encoding of moers_complex is
	signal count: integer:= 0;
	signal index: integer:=0;
    signal lock: integer:=0;
begin

	process(clk, clock, rst)
	begin
		 if (rst = '1') then
					state <= "00000";
					count <= 0;
					index <= 0;
					long <= '0';
					short <= '0';
					display <= "0000";
        elsif (rising_edge(clock) and clk='1') then
            if (count = 1000000 and lock = 0) then
                count <= 0;
                lock <= 1;
                long <= '1';
                short <= '0';
            else
                if (lock = 0) then
			        count <= count + 1;
                    long <= '0';
                    short <= '1';
                end if;
            end if;

		elsif (rising_edge(clock) and clk='0') then
            if (long /= short) then
                case index is
                    when 0 | 1 | 2 | 3 | 4 =>
                        if (long = '1') then
                            state(index) <= '1';
                        else
                            state(index) <= '0';
                        end if;
                        index <= index + 1;
                    when others => NULL;
                end case;

                lock <= 0;
                count <= 0;
                long <= '0';
                short <= '0';

            end if;

            case index is
                when 5 =>
                    index <= 0;
                    case state is
                        when"11110"=>display<="0001";
                        when"11100"=>display<="0010";
                        when"11000"=>display<="0011";
                        when"10000"=>display<="0100";
                        when"00000"=>display<="0101";
                        when"00001"=>display<="0110";
                        when"00011"=>display<="0111";
                        when"00111"=>display<="1000";
                        when"01111"=>display<="1001";
                        when"11111"=>display<="0000";
                        when others=>display<="1111";
                    end case;
                when others => NULL;
            end case;
		end if;
	end process;
end encoding;
```