# 毫秒表

[毫秒表.doc](%E6%AF%AB%E7%A7%92%E8%A1%A8%20e464e9ed15de4c13b991a90cd3c8c7e5/%E6%AF%AB%E7%A7%92%E8%A1%A8.doc)

```vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_down is
port(
	clock : in std_logic;
	clk : in std_logic;
	rst : in std_logic;
	input_num : in std_logic_vector(3 downto 0);
	output_num : out std_logic_vector(3 downto 0);
	output_second : out std_logic_vector(3 downto 0)
);
end count_down;
architecture behave of count_down is
signal status : integer := 0; -- 0 代表设置，1代表倒计时
signal current_num : std_logic_vector(3 downto 0) :="0000";
signal current_second : std_logic_vector(3 downto 0) := "0000";-- 毫秒计时器
signal counter : integer := 0;
begin 

process(clock, clk, rst)
begin
	if(clock='1' and clock'event) then
		if(rst='1') then
			status<=0;
			current_num<=input_num;
			current_second<="0000";
		elsif(clk='1') then
			status<=1;
			current_num<=input_num;
			current_second<="0000";
		elsif(status=1) then
			if(counter=100000) then
				counter<=0;
				if(current_second/="0000") then
					current_second<=current_second - 1;
				else
					if(current_num/="0000") then
						current_num<=current_num - 1;
						current_second<="1001";
					end if;
				end if;
			else
				counter <= counter + 1;
			end if;
		elsif(status=0) then
			current_num<=input_num;
			current_second<="0000";
		end if;
	end if;
end process;

output_num<=current_num; -- 秒
output_second<=current_second; -- 毫秒

end behave;
```