# 记数器

- D 触发器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity myDFF is
-- 正边沿D触发器
	 port(
		  D, CP, Rd, Sd: in std_logic ;
		  Q: out std_logic :='0';
		  nQ: out std_logic :='1'
	 );
end myDFF;

architecture arch of myDFF is
begin
	 process(Rd, Sd, CP)
		 begin
		 if (Rd = '0') then
			  Q <= '0';
			  nQ <= '1';
		 elsif (Sd = '0') then
			  Q <= '1';
			  nQ <= '0';
		 elsif (CP'event and CP = '1') then
			  Q <= D;
			  nQ <= not D;
		 end if ;
	 end process ;
end arch;
```

- 六进制计数器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_6 is
	 port(
		 clk, Rd, c0: in std_logic ;
		 out_6: out std_logic_vector(3 downto 0)
	 );
end clock_6;

architecture clock_6_bhv of clock_6 is
  component myDFF is
	 port(
	 D, CP, Rd, Sd: in std_logic ;
	 Q: out std_logic := '0';
	 nQ: out std_logic := '1'
	 );
  end component;
  signal D, Q, nQ: std_logic_vector(2 downto 0);
begin
	 lb0: for i in 0 to 2 generate
		Di: myDFF port map(D(i), clk , Rd, '1', Q(i), nQ(i));
	 end generate lb0;
	 D(0) <= c0 xor Q(0);
	 D(1) <= ((not c0) and Q(1)) or (c0 and (nQ(2) and (Q(1) xor Q(0))));
	 D(2) <= ((not c0) and Q(2)) or (c0 and ((Q(2) and nQ(0)) or (Q(1) and Q(0))));
	 out_6(2 downto 0) <= Q;
	 out_6(3) <= '0';
end clock_6_bhv;
```

- 十进制计数器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_10 is
 port(
	 clk , Rd: in std_logic ;
	 out_10: out std_logic_vector(3 downto 0)
	 );
 end clock_10;

architecture clock_10_bhv of clock_10 is
	 component myDFF is
	 port(
		 D, CP, Rd, Sd: in std_logic ;
		 Q: out std_logic := '0';
		 nQ: out std_logic := '1'
	 );
	 end component;
	 signal D, Q, nQ: std_logic_vector(3 downto 0);
begin
	 lb0: for i in 0 to 3 generate
			dt: myDFF port map(D(i), clk , Rd, '1', Q(i), nQ(i));
	 end generate lb0;
		 D(0) <= nQ(0);
		 D(1) <= (nQ(0) xor nQ(1)) and (Q(0) nand Q(3));
		 D(2) <= ((not Q(0)) or (not Q(1))) xnor Q(2);
		 D(3) <= ((not ((nQ(0) or nQ(1) or nQ(2))) xnor nQ(3)) and (Q(0) nand Q(3)));
		 out_10 <= Q;
 end clock_10_bhv;
```

- 六十进制计数器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_60 is
	 port(
		 clk , rst : in std_logic ;
		 low, high: out std_logic_vector(3 downto 0)
	 );
end clock_60;

architecture clock_60_bhv of clock_60 is
	 component myDFF
		 port(
			 D, CP, Rd, Sd: in std_logic ;
			 Q: out std_logic := '0';
			 nQ: out std_logic := '1'
		 );
	 end component;
	 
	 component clock_6
		 port(
			 clk , Rd, c0: in std_logic ;
			 out_6: out std_logic_vector(3 downto 0)
		 );
	 end component;
	 
	 component clock_10
		 port(
		 clk , Rd: in std_logic ;
		 out_10: out std_logic_vector(3 downto 0)
		 );
	 end component;
	 
	 signal D, c0, Rd: std_logic ;
	 signal QL, QH: std_logic_vector(3 downto 0);
begin
	 count_low: clock_10 port map(clk, Rd, QL);
	 count_high: clock_6 port map(clk, Rd, c0, QH);
	 trriger: myDFF port map(D, clk, Rd, '1', c0);
	 Rd <= not rst;
	 D <= (QL(3) and (not QL(2))) and ((not QL(1)) and (not QL(0)));
	 low <= QL;
	 high <= QH;
end clock_60_bhv;
```

- 译码器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity digit_7 is
	port(
		number: in std_logic_vector(3 downto 0);
		display: out std_logic_vector(6 downto 0)
	);
end digit_7;
architecture arch of digit_7 is
begin
	process(number)
	begin
		case number is
			when "0000"=>display<="1111110";
			when "0001"=>display<="0110000";
			when "0010"=>display<="1101101";
			when "0011"=>display<="1111001";
			when "0100"=>display<="0110011";
			when "0101"=>display<="1011011";
			when "0110"=>display<="0011111";
			when "0111"=>display<="1110000";
			when "1000"=>display<="1111111";
			when "1001"=>display<="1110011";
			when "1010"=>display<="1110111";
			when "1011"=>display<="0011111";
			when "1100"=>display<="1001110";
			when "1101"=>display<="0111101";
			when "1110"=>display<="1001111";
			when "1111"=>display<="1000111";
			when others=>display<="0000000";
		end case;
	end process;
end arch;
```

- 带译码的六十进制加法计数器

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock is
	 port(
		 clk , rst : in std_logic ;
		 lout , hout: out std_logic_vector
		 );
	 end clock;

architecture clock_bhv of clock is
	 component clock_60
		 port(
			 clk , rst : in std_logic ;
			 low, high: out std_logic_vector(3 downto 0)
		 );
	 end component;
	 component digit_7
		 port(
			 number: in std_logic_vector(3 downto 0);
			 display: out std_logic_vector(6 downto 0)
		 );
	 end component;
	 signal low, high: std_logic_vector(3 downto 0);
begin
	 count: clock_60 port map(clk, rst, low, high);
	 digit_low: digit_7 port map(low, lout);
	 digit_high: digit_7 port map(high, hout);
end clock_bhv;
```

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count is
	 port(
		 clk , rst , pause: in std_logic ;
		 lout , hout: out std_logic_vector(6 downto 0)
	 );
end count;

architecture count_bhv of count is
	 component clock
		 port(
			 clk , rst : in std_logic ;
			 lout , hout: out std_logic_vector(6 downto 0)
		 );
	 end component;
	 signal clk2 : std_logic := '0';
	 signal t: integer := 0;
begin
	 main_count: clock port map(clk2, rst , lout , hout);
	 process(pause, clk , rst )
		 begin
		 if ( rst = '1') then
			 t <= 0;
			 clk2 <= '0';
		 elsif (clk 'event and clk = '1' and pause = '0') then
			 if (t = 1000000) then
				 t <= 0;
				 clk2 <= '1';
			 elsif (t = 500000) then
				 t <= t + 1;
				 clk2 <= '0';
			 else
				 t <= t + 1;
			 end if ;
		 end if ;
	 end process ;
end count_bhv;
```